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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75218
4-BIT SINGLE-CHIP MICROCOMPUTER
The PD75218 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, ROM, RAM, I/O ports, an FIP controller/driver, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM pulses, a serial interface and a vectored interrupt function integrated on a single chip. It is most suitable for applications which use fluorescent display tubes as display devices and require the timer/ watch function and high-speed interrupt servicing, such as VCR, CD and ECR. It can help to provide the unit with many functions and to decrease performance costs. The PD75218 has larger ROM and RAM capacity than its predecessor, PD75217. So several codes required before have been reduced to only one code in the PD75218 specifications. The one-time PROM product, PD75P218 and various development tools (IE-75001-R, assembler, etc.) are available for system development evaluation or small production. The following manual provides detailed description of the functions of the PD75218. Be sure to read this manual when you design an application system. PD75218 User's Manual: IEU-692
FEATURES
* On-chip large-capacity ROM and RAM * Program memory (ROM) : 32K x 8 bits * Data memory (RAM) : 1K x 4 bits * Architecture equal to that of an 8-bit microcomputer * High-speed operation: Minimum instruction execution time : 0.67 s (when the microcomputer operates at 6.0 MHz) * Instruction execution time variable function realizing a wide range of operating voltages * On-chip programmable fluorescent indication panel (FIP) controller/driver * Timer function : 4 ch * 14-bit PWM output capability with the voltage synthesizer type electronic tuner * Buzzer output capability * Interrupt function with importance attached to applications * For power-off detection * For reception of remote-controller signal * Product with an on-chip PROM : PD75P218 (on-chip EPROM : WQFN package)
The information in this document is subject to change without notice. Document No. IC-3035 (O. D. No. IP-8484) Date Published November 1993 P Printed in Japan Major changes in this version are indicated by stars (5) in the margins.
(c) NEC Corporation 1993
PD75218
ORDERING INFORMATION
Part number Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 x 20 mm) Quality grade Standard Standard
PD75218CW-xxx PD75218GF-xxx-3BE
Remark xxx is a ROM code.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications
LIST OF FUNCTIONS
Item Built-in memory I/O line (including FIP (R) dualfunction pins and excluding FIP dedicated pins) Instruction cycle ROM: 32640 x 8 bits, RAM: 1024 x 4 bits * * 33 lines * * CMOS input : 8 lines CMOS I/O : 20 lines (LED drive: 8 lines) CMOS output : 1 line (PWM/pulse output)
P-ch open-drain output with high withstand voltage and high current: 4 lines (LED drive)
Function
* 0.67 s, 1.33 s, 10.7 s (with main system clock operating at 6.0 MHz) * 0.95 s, 1.91 s, 15.3 s (with main system clock operating at 4.19 MHz) * 122 s (with subsystem clock operating at 32.768 kHz) * * * * * Number of segments : 9 to 16 segments Number of digits : 9 to 16 digits Dimmer function : 8 levels Mask option for pull-down resistors Key scan interrupt generation * * * * Timer/pulse generator : 14-bit PWM output enabled Watch timer : Buzzer output enabled Timer/event counter Basic interval timer : Watchdog timer application capability
FIP controller/driver
Timer 4 channels
Serial interface Vectored interrupt Test input System clock oscillator
* MSB start/LSB start switchable * Serial bus configuration capability External : 3, Internal : 5 External : 1, Internal : 1 * Ceramic/crystal oscillator for main system clock oscillation : 6.0 MHz standard * Ceramic/crystal oscillator for main system clock oscillation : 4.19 MHz standard * Crystal oscillator for subsystem clock oscillation : 32.768 kHz standard * High withstand-voltage port (pull-down resistor) * Port 6 (pull-down resistor) -40 to +85 C 2.7 to 6.0 V (standby data hold : 2.0 to 6.0 V) * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm)
Mask option Operating temperature range Operating supply voltage Package
2
PD75218
CONTENTS 1. 2. 3. PIN CONFIGURATION (TOP VIEW) ......................................................................................... BLOCK DIAGRAM ...................................................................................................................... PIN FUNCTIONS ........................................................................................................................
3.1 3.2 3.3 3.4 3.5 3.6 PORT PINS ...................................................................................................................................... NON-PORT PINS ............................................................................................................................ PIN INPUT/OUTPUT CIRCUIT LIST .............................................................................................. HANDLING UNUSED PINS ........................................................................................................... NOTES ON USE OF THE P00/INT4 PIN AND RESET PIN ......................................................... NOTES ON USE OF THE XT1, XT2 AND P50 PIN ......................................................................
5 6 7
7 8 9 10 11 11
4. 5.
MEMORY CONFIGURATION .................................................................................................... PERIPHERAL HARDWARE FUNCTIONS ..................................................................................
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 PORTS .............................................................................................................................................. CLOCK GENERATOR ...................................................................................................................... BASIC INTERVAL TIMER ............................................................................................................... WATCH TIMER .............................................................................................................................. TIMER/EVENT COUNTER ............................................................................................................. TIMER/PULSE GENERATOR ......................................................................................................... SERIAL INTERFACE ....................................................................................................................... FIP CONTROLLER/DRIVER ............................................................................................................
12 15
15 16 17 18 19 20 21 23
6. 7. 8. 9.
INTERRUPT FUNCTIONS .......................................................................................................... STANDBY FUNCTIONS ............................................................................................................. RESET FUNCTIONS ................................................................................................................... INSTRUCTION SET ....................................................................................................................
24 26 27 29 38 39
39 40 41
10. MASK OPTION SELECTION ...................................................................................................... 11. APPLICATION BLOCK DIAGRAM .............................................................................................
11.1 11.2 11.3 VCR TIMER TUNER ........................................................................................................................ COMPACT DISK PLAYER .............................................................................................................. ECR ...................................................................................................................................................
3
PD75218
5
12. ELECTRICAL SPECIFICATIONS ............................................................................................... 13. CHARACTERISTIC CURVES (FOR REFERENCE) ..................................................................... 14. PACKAGE DIMENSIONS ........................................................................................................... 15. RECOMMENDED SOLDERING CONDITIONS ........................................................................ APPENDIX A APPENDIX B FUNCTIONS OF PD752xx SERIES PRODUCTS ................................................ DEVELOPMENT TOOLS ......................................................................................... RELATED DOCUMENTS ........................................................................................
42 53 55 57 58 59 60
5
5
APPENDIX C
4
PD75218
1. PIN CONFIGURATION (TOP VIEW)
S3 S2 S1 S0 P00/INT4 P01/SCK P02/SO P03/SI P10/INT0 P11/INT1 P12/INT2 P13/TI0 P20 P21 P22 P23/BUZ P30 P31 P32 P33 P60 P61 P62 P63 P40 P41 P42 P43 PPO X1 X2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD S4 S5 S6 S7 S8 S9 VPRE VLOAD T15/S10 T14/S11 T13/S12/PH0 T12/S13/PH1 T11/S14/PH2 T10/S15/PH3 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 RESET P53 P52 P51 P50 XT2 XT1
P12/INT2
P11/INT1
P10/INT0
P23/BUZ
P13/TI0
P41 P42 P43 PPO X1 X2 VSS XT1 XT2 P50 P51 P52 P53
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 32 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 31 30 29 28 27 26 25 24 23 22 21 20 9 10 11 12 13 14 15 16 17 18 19
P02/SO
P03/SI
PD75218CW-x x x
P40
P63
P62
P61
P60
P33
P32
P31
P30
P22
P21
P20
P01/SCK P00/INT4 S0 S1 S2 S3 VDD S4 S5 S6 S7 S8 S9
PD75218GF-x x x-3BE
T10/S15/PH3
T11/S14/PH2
T12/S13/PH1
T13/S12/PH0
T14/S11
T15/S10
RESET
VLOAD
VPRE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
5
SCK/P01 INTSIO
INT0/P10 INT1/P11 INT2/P12 Interrupt control
INT4/P00
6
Port 0 Basic interval timer CY SP(8) SBS(4) Port 2 Timer/event counter #0 Bank 4 P20-P23 4 P00-P03 Port 1 Program counter (15) ALU 4 P10-P13 INTBT TI0/P13 Port 3 4 P30-P33 INTT0 Timer/pulse generator PPO INTTPG SI/P03 SO/P02 Serial interface ROM Program memory 32640 x 8 bits Decode and control Port 6 RAM Data memory 1024 x 4 bits 4 P60-P63 Port 4 General register 4 P40-P43 Port 5 4 P50-P53 10 T0-T9 4 FIP controller/ driver 2 T14/S11, T15/S10 S0-S9 VPRE VLOAD 10 INTW fX/2 N System clock generator Sub Main CPU clock INTKS Watch timer Clock divider Standby control Port H BUZ/P23 XT1 XT2 X1 X2 VDD VSS RESET 4 PH0-PH3
T10/S15/PH3- T13/S12/PH0
2. BLOCK DIAGRAM
PD75218
PD75218
3. PIN FUNCTIONS
3.1 PORT PINS
Pin P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 to P33
I/O Input Input/output Input/output Input Input
Dualfunction pin INT4 SCK SO SI INT0 INT1 INT2 TI0
Function 4-bit input port (PORT0)
8-bit I/O
After reset Input
Input / output circuit typeNote B F G B
x
Noise elimination function available Noise elimination function available 4-bit input port (PORT1)
Input
B
Input/ output
--- --- --- BUZ
4-bit input/output port (PORT2)
x
Input
E
Input/ output Input/ output Input/ output Input/ output
---
Programmable 4-bit input/ output port (PORT3). Input/output specifiable in 1-bit units. 4-bit input/output port (PORT4). LED direct drive capability. 4-bit input/output port (PORT5). LED direct drive capability. Programmable 4-bit input/output port (PORT6). Input/output specifiable in 1-bit units. On-chip pull-down resistor available (mask option). Suitable for key input.
Input
E
P40 to P43
---
q
Input
E
P50 to P53
---
Input
E
P60 to P63
---
x
Input
V
PH0 PH1 PH2 PH3
Output
T13/S12 T12/S13 T11/S14 T10/S15
4-bit P-ch open-drain output port with high withstand voltage and high current (PORTH). LED direct drive capability. On-chip pull-down resistor available (mask option).
x
Low level (with an onchip pulldown resistor) or high impedance.
I
Note
The circuit-type codes enclosed in circles indicate that the corresponding circuits have a Schmitt-triggered input.
7
PD75218
3.2
NON-PORT PINS
Dualfunction pin --- FIP controller/ driver output pins. Pull-down resistor can be incorporated in bit units (mask option). Input / output circuit typeNote I
Pin T0 to T9
I/O Output
Function
After reset
T10/S15 to T13/S12
PH3 to PH0
T14/S11, T15/S10
---
Output pins with high withstand voltage Low level (with an onand high current for digit output chip pullOutput pins with high withstand voltage down and high current also used for digit/seg- resistor ) or high ment output impedance Extra pins can be used as PORTH. (without a pull-down Output pins with high withstand voltage resistor) and high current also used for digit/ segment output Static output also possible. High withstand-voltage output for segment output. Static output also possible. High withstand-voltage output for segment output
S9
S0 to S8
PPO
Output
---
Timer/pulse generator pulse output
High impedance --- Input Input Input ---
D
TI0 SCK SO SI INT4
Input Input/output Input/output Input Input
P13 P01 P02 P03 P00
External event pulse input for timer/event counter Serial clock input/output Serial data output or serial data input/output Serial data input or normal input Edge-detected vectored interrupt input (rising and falling edge detection). Edge-detected vectored interrupt input with noise elimination function (detection edge selection possible). Edge-detected testable input (rising edge detection). Fixed frequency output (for buzzer or system clock trimming). Crystal/ceramic connection pin for main system clock oscillation. External clock input to X1 and its inverted clock input to X2. Crystal connection pin for subsystem clock oscillation. External clock input to XT1. Leave XT2 open. System reset input (low level active). FIP controller/driver output buffer power supply. FIP controller/driver pull-down resistor connection pin. Positive power supply. GND potential.
B F G B B
INT0 INT1 INT2 BUZ
Input
P10 P11
---
B
Input Input/output
P12 P23
--- Input
B E
X1 X2
Input ---
---
---
---
XT1 XT2 RESET
Input --- Input --- --- --- ---
---
---
---
--- --- --- --- ---
--- --- --- --- ---
B I I --- ---
5
VPRE VLOAD VDD VSS
Note
The circuit-type codes enclosed in circles indicate that the corresponding circuits have a Schmitt-triggered input.
8
PD75218
3.3
PIN INPUT/OUTPUT CIRCUIT LIST
Type A Type F
VDD
Data Output disable Type D
IN/OUT
P-ch IN N-ch
Type B
CMOS-specified input buffer Type B
Input/output circuit consisting of type D push-pull output and type B schmitt trigger input Type G VDD P-ch output disable Data P-ch IN/OUT N-ch Type B
IN
Schmitt trigger input having hysteresis characteristics Type D VDD Data Data P-ch OUT Output disable Type D IN/OUT Input/output circuit capable of switching between push-pull output and N-ch open-drain output (with P-ch off). Type V
Output disable
N-ch Type A Pull-down resistor (Mask option)
Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) Type E Type I
Data Output disable Type D
VDD IN/OUT Data P-ch
VDD P-ch
OUT
N-ch Type A
Pull-down resistor (Mask option) VLOAD VPRE
Input/output circuit consisting of type D push-pull output and type A input buffer
9
PD75218
3.4
HANDLING UNUSED PINS
Pin P00/INT4 P01/SCK P02/SO P03/SI P10/INT0 to P12/INT2 P13/TI0 P20 to P22 P23/BUZ P30 to P33 P40 to P43 P50 to P53 P60 to P63 PPO S0 to S9 T15/S10 to T14/S11 T0 to T9 T10/S15/PH3 to T13/S12/PH0 XT1 XT2 VLOAD when there is no onchip load resistor Leave open Connect to VSS Connect to VSS
Recommended connection
Connect to VSS or VDD
Input state : Connect to VSS or VDD Output state : Leave open
Connect to VSS or VDD Leave open Connect to VSS or VDD
10
PD75218
3.5 NOTES ON USE OF THE P00/INT4 PIN AND RESET PIN P00/INT4 and RESET pins have the function (especially for IC test) to test PD75218 internal operations in addition to the functions described in sections 3.1 and 3.2. The test mode is set when a voltage larger than VDD is applied to one of these pins. If noise larger than VDD is applied in normal operation, the test mode may be set thereby adversely affecting normal operation. Since there is a display output pin having a high-voltage amplitude (35 V) next to the P00/INT4 and RESET pins, if cables for the related signals are routed in parallel, wiring noise larger than VDD may be applied to the P00/INT4 and RESET pins causing errors. Thus, carry out wiring so that wiring noise can be minimized, If noise still cannot be suppressed, take the measure against noise using the following external components. * Connecting a diode between the pins and VDD
VDD
*
Connecting a capacitor between the pins and VDD
VDD
VDD
VDD
P00/INT4, RESET
P00/INT4, RESET
3.6 NOTES ON USE OF THE XT1, XT2 AND P50 PIN When selecting the 32.768 kHz subsystem clock connected to the XT1 and XT2 pins as the watch timer source clock, the signal to be input or output to the P50 pin next to the XT2 pin must be a signal required to be switched between high and low the minimum number of times (once/second or less). If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch becomes fast). If it is necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the P50 pin as shown below.
PD75218
P50 XT1 XT2 0.0068 F 32.768 kHz
11
PD75218
4. MEMORY CONFIGURATION
* Program memory (ROM): 32640 words x 8 bits
* 0000H and 0001H: Vector table which contains the program start address after reset * 0002H to 000FH : Vector table which contains the program start addresses when interrupts occur * 0020H to 007FH : Table area referenced by a GETI instruction
* Data memory
* Data area : 1024 words x 4 bits (000H to 3FFH) * Peripheral hardware area : 128 words x 4 bits (F80H to FFFH)
12
PD75218
Fig. 4-1 Program Memory Map
0000H MBE RBE Internal reset start address (high-order 6 bits) Internal reset start address (low-order 8 bits) 0002H MBE RBE INTBT/INT4 start address INTBT/INT4 start address 0004H MBE RBE INT0 start address INT0 start address 0006H MBE RBE INT1 start address INT1 start address 0008H MBE RBE INTSO start address INTSO start address 000AH MBE RBE INTT0 start address INTT0 start address 000CH MBE RBE INTTPG start address INTTPG start address 000EH MBE RBE INTKS start address INTKS start address (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) Branch address specified in BR !addr instruction 0020H GETI instruction reference table 007FH 0080H Branch address specified in CALL !addr instruction Branch/call address specified in GETI instruction Branch address specified in BRCB !caddr instruction Branch address specified in CALLA !addr instruction Relative branch address specified in BR $addr instruction (-15 to -1, +2 to +16) Entry address specified in CALLF !faddr instruction Branch address specified in BRA !addr instruction
07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H
Branch address specified in BRCB !caddr instruction Branch address specified in BRCB !caddr instruction Branch address specified in BRCB !caddr instruction Branch address specified in BRCB !caddr instruction Branch address specified in BRCB !caddr instruction Branch address specified in BRCB !caddr instruction Branch address specified in BRCB !caddr instruction
3FFFH 4000H 4FFFH 5000H
5FFFH 6000H
6FFFH 7000H 7F7FH
Caution The start address of an interrupt vector shown above consists of 14 bits. So the start address must be set within a 16K-byte space (0000H to 3FFFH). Remark In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC changed is enabled by BR PCDE and BR PCXA instructions.
13
PD75218
Fig. 4-2 Data Memory Map
Data memory General register area 000H (32 x 4) 01FH 020H 256 x 4 0FFH 100H Stack area Display data memory, etc. 1BFH 1C0H (64 x 4) 1FFH 200H 256 x 4
Memory bank
0
1
Data area Static RAM (1024 x 4)
256 x 4
2
2FFH 300H
256 x 4
3
3 FFH Not contained
F80H Peripheral hardware area FFFH 128 x 4 15
14
PD75218
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS The PD75218 has the following three types of I/O port: * 8 CMOS input pins (PORT0 and PORT1) * 20 CMOS I/O pins (PORT2, PORT3, PORT4, PORT5, and PORT6) * 4 P-ch open-drain output pins with high withstand voltage and high current (PORTH) Total: 32 pins Table 5-1 Functions of Ports
Port PORT0
Function 4-bit input
Operation and feature Always read or test possible irrespective of the dual-function pin operating mode. Always read or test possible, P10 and P11 are inputs with the noise elimination function.
Remarks Shares the pins with SI, SO, SCK and INT4. Shares the pins with INT0 to INT2 and TI0. P23 shares the pin with BUZ.
PORT1
PORT2 PORT4 PORT5 PORT3 PORT6 PORTH
4-bit input/output
Can be set to the input or output mode in 4-bit units. Ports 4 and 5 can input/output data in pairs in 8-bit units. Ports 4 and 5 can directly drive LEDs. Can be set bit-wise to the input or output mode. Port 6 can incorporate a pull-down resistor by mask option.
4-bit output
P-ch open-drain output port with high withstand voltage and high current. Can drive an FIP and LED directly. Can incorporate a pull-down resistor in bit units by mask option.
Shares the pins with T10/S15 to T13/S12.
15
PD75218
5.2 CLOCK GENERATOR Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control register (SCC). The main system clock or subsystem clock can be selected. The instruction execution time is variable. 0.67 s, 1.33 s, 10.7 s (main system clock: 6.0 MHz) 0.95 s, 1.91 s, 15.3 s (main system clock: 4.19 MHz) 122 s (subsystem clock: 32.768 kHz) Fig. 5-1 Clock Generator Block Diagram
XT1 Subsystem clock generator fXT Watch timer Timer/pulse generator Main system clock generator Selector 1/8 to 1/4096 fXX Frequency divider 1/2 1/6 SCC SCC3 Selector SCC0 PCC Internal bus PCC0 Oscillation stop Frequency divider 1/4 * FIP controller * Basic interval timer (BT) * Timer/event counter * Serial interface * Watch timer * INT0 noise eliminator
XT2 X1
X2
fX
* CPU * INT0 noise eliminator * INT1 noise eliminator
PCC1 4 HALT F/F HALTNote STOPNote PCC2 PCC3 R Q S
PCC2 and PCC3 clear
STOP F/F Q S
Wait release signal from BT
RES signal (internal reset)
Note
Instruction execution
R Standby release signal from interrupt control circuit
Remarks 1. fX = Main system clock frequency 2. fXT = Subsystem clock frequency 3. fXX = System clock frequency 4. 5. 6. 7.
5
= CPU clock PCC: Processor clock control register SCC: System clock control register 1 clock cycle (tCY) of is 1 machine cycle of an instruction. For tCY, see "AC Characteristics" in Chapter 12.
16
PD75218
5.3 BASIC INTERVAL TIMER The basic interval timer has the following functions: * * * * Interval timer operation to generate reference time Watchdog timer application to detect inadvertent program loop Wait time select and count upon standby mode release Count contents read Fig. 5-2 Basic Interval Timer Configuration
From clock generator Clear fXX/25 fXX/27 MPX fXX/29 fXX/212 BT IRQBT Basic interval timer (8-bit frequency divider) Clear
Set
BT interrupt request flag
Vectored interrupt request signal
3 Wait release signal during standby release
BTM3
BTM2
BTM1
BTM0
BTM
SET1Note
4 Internal bus
8
Note
Instruction execution
17
PD75218
5.4 WATCH TIMER The PD75218 incorporates one channel of watch timer. The watch timer has the following functions: * Sets the test flag (IRQW) at 0.5 sec intervals. The standby mode can be released by IRQW. * 0.5 second interval can be set with the main system clock and subsystem clock. * The fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection. * The fixed frequencies (2.048 kHz) can be output to the P23/BUZ pin for use to generate buzzer sound and trim the system clock oscillator frequency. * Since the frequency divider can be cleared, the watch can be started from zero second. Fig. 5-3 Watch Timer Block Diagram
fW (256 Hz : 3.91 ms) 7 2 fXX 128 (32.768 kHz) fXT (32.768 kHz) Selector INTW IRQW set signal
From clock generator
Selector
fW
(32.768 kHz)
fW 14 2 Frequency divider 2 Hz 0.5 sec fW 16 (2.048 kHz) Clear
Output buffer P23/BUZ
WM WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0
PORT2.3 P23 output latch
Bit 2 of PMGB Port 2 input/output mode
8
Internal bus
Remark
Values when fXX is 4.194304 MHz and fXT is 32.768 kHz are indicated in parentheses.
Caution When the main system clock operates at 6.0 MHz, a time interval of 0.5 second cannot be produced. Before producing this time interval, the main system clock must be changed to the subsystem clock.
18
PD75218
5.5 TIMER/EVENT COUNTER The PD75218 incorporates one channel of timer/event counter. The timer/event counter has the following functions: * Program interval timer operation * Event counter operation * Count state read function Fig. 5-4 Timer/Event Counter Block Diagram
Internal bus SET1Note 8
TM0
8 8 Modulo register (8) TMOD0
TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0
8 Comparator (8) Input buffer 8 T0 P13/TI0 From clock generator (See Fig. 5-1.) MPX Count register (8) CP Clear Timer operation start
Match INTT0 IRQT0 set signal
IRQT0 clear
Note
Instruction execution
19
PD75218
5.6 TIMER/PULSE GENERATOR The PD75218 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse generator. The timer/pulse generator has the following functions: (a) Functions available in the timer mode * 8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels * Square wave output to PPO pin Functions available in the PWM pulse generation mode * 14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to-analog converter and applicable to tuning) 2 15 * Fixed time interval ( = 5.46 ms when the microcomputer operates at 6.0 MHz)Note interrupt generation fX
(b)
If pulse output is not necessary, the PPO pin can be used as a 1-bit output port. Note 7.81 ms when the microcomputer operates at 4.19 MHz
Caution If the STOP mode is set while the timer/pulse generator is in operation, erroneous operation may result. To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode register. Fig. 5-5 Block Diagram of Timer/Pulse Generator (Timer Mode)
Internal bus
8 MODL Modulo register L (8) TPGM3 (Set to 1)
8 MODH Modulo register H (8)
Modulo latch H (8) 8 Match Comparator (8) Frequency divider fX 1/2 TPGM1 Prescalar select latch (5) Clear T F/F Set Selector
INTTPG IRQTPG set signal
Output buffer
PPO CP 8 Count register (8) Clear
TPGM4 TPGM5 TPGM7
20
PD75218
Fig. 5-6 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode)
Internal bus
8 MODH Modulo register H (8) TPGM3
8 MODL Modulo register L (8) (2)
MODH (8) Modulo latch (14)
MODL7-2 (6) Output buffer
TPGM1 fX 1/2
PWM pulse generator
Selector
PPO
Frequency divider INTTPG TPGM5 (IRQTPG set signal) 15 2 ( = 5.46 ms : when fX is 6.0 MHz)Note fX
TPGM7
Note
7.81 ms when the microcomputer operates at 4.19 MHz.
5.7 SERIAL INTERFACE The serial interface has the following functions: * Clock synchronous 8-bit send/receive operation (simultaneous send/receive) * Clock synchronous 8-bit serial bus operation (data input/output from the SO pin. N-ch open-drain SO output) * Start LSB/MSB switching These functions facilitate data communication with another microcomputer of PD7500 series or 78K series via a serial bus and coupling with peripheral devices.
21
Selector
22
8 P03/SI 8 SIO0 Shift register (8)
Note 1
Fig 5-7 Serial Interface Block Diagram
Internal bus
8 SIO7 SIO
SET1Note 2 SIOM
SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0
P02/SO
SO output latch
Serial clock counter (3)
Overflow
INTSIO IRQSIO set signal IRQSIO clear signal
Clear P01/SCK R Q S
Serial start
fXX/24 MPX fXX/210
Notes 1. 2.
CMOS output and N-ch open-drain output switchable output buffer. Instruction execution
PD75218
PD75218
5.8 FIP CONTROLLER/DRIVER The FIP controller/driver in the PD75218 has the same functions as that in its predecessor, PD75216A:
* The FIP controller/driver outputs the segment signal by automatically reading display data (DMA operation)
and automatically generates the digit signal.
* The FIP controller/driver can control the FIP of 9 to 16 segments and 9 to 16 digits with the display mode register
(DSPM) and the digit select register (DIGS) (within the range of up to 26 display outputs).
* The display outputs unused for dynamic display can be used as static outputs. * The dimmer function provides eight levels of intensity. * Such hardware is contained that a key scan application is possible.
* * A * * A A key scan interrupt (IRQKS) is caused. (A key scan timing is detected.) Key scan data can be output from key scan registers (KS0 and KS1) onto a segment output pin. high-voltage output pin (40 V) is provided which can directly drive the FIP. Pins dedicated to segments (S0 to S9): VOD = 40 V, IOD = 3 mA Digit output pins (T0 to T15): VOD = 40 V, IOD = 15 mA mask option enables a pull-down resistor to be incorporated for each bit. Fig. 5-8 FIP Controller/Driver Block Diagram
*
*
Internal bus 4 Display mode register 4 Digit select register 4 Dimmer select register Key scan flag (KSF)
Display data memory (64 x 4 bits)
Key scan registers (KS0 and KS1) 12
Port H 4 Digit signal generator 4 4
Segment data latch (16)
IRQKS generation signal
Selector 10 2 2 4 4
Selector 2 4 10
Output buffer with a high withstand voltage 10 S0-S9 2 T15/S10 and T14/S11 4 T13/S12/PH0T10/S15/PH3 10 T0-T9 VLOAD VPRE
Caution The FIP controller/driver can only operate at the high and intermediate speeds (PCC = 0011B or 0010B) of the main system clock (SCC.0 = 0). It may cause errors with any other clock or in the standby mode. Thus, be sure to stop FIP controller operation (DSPM.3 = 0) and then shift the unit to any other clock mode or the standby mode. 23
PD75218
6. INTERRUPT FUNCTIONS
The PD75218 has eight types of interrupt sources and can generate multiple interrupts with priority order. It is also equipped with two types of test sources. INT2 is an edge detected testable input. The PD75218 interrupt control circuit has the following functions: * Hardware-controlled vectored interrupt function which can control interrupt acknowledge with the interrupt enable flag (IExxx) and the interrupt master enable flag (IME). * Function of setting any interrupt start address. * Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS). * Interrupt request flag (IRQxxx) test function. (Interrupt generation can be checked by software.) * Standby mode release function (Interrupts to be released can be selected by interrupt enable flags.)
24
Fig. 6-1 Interrupt Control Circuit Block Diagram
Internal bus 2 IM1 2 IM0 (IME) Interrupt enable flag (IEXXX) Decoder IRQBT IRQ4 IRQ0 IRQ1 IRQSIO IRQT0 IRQTPG IRQKS IRQW IRQ2 Standby release signal Priority control circuit Vector table address generator circuit VRQn 4 IPS 2 IST
INT BT INT4/ P00 INT0/ P10 INT1/ P11
Note
Both edges detection circuit Edge detection circuit Edge detection circuit
Note
INTSIO INTT0 INTTPG INTKS INTW INT2/ P12
Rising edge detection circuit
Note
Noise eliminator
PD75218
25
PD75218
7. STANDBY FUNCTIONS
Two standby modes (STOP mode and HALT mode) are available for the PD75218 to decrease power consumption in the program standby mode. Table 7-1 Operation Status in Standby Mode
STOP mode Set instruction System clock when set STOP instruction Setting enabled only for main system clock Oscillator stops only for main system clock Operation stopped HALT mode HALT instruction Setting enabled for either main system clock or subsystem clock Stops only for CPU clock (oscillation continued) Operation continued (IRQBT set at reference time intervals) Operation enabled when serial clock other than is specified Operation enabled
Clock oscillator
Basic interval timer
Operating State
Serial interface
Operation enabled only when external SCK input is selected for serial clock Operation enabled only when TI0 pin input is specified for count clock Operation stopped
Timer/event counter
Timer/pulse generator Watch timer
Operation enabled
Operation enabled only fXT is selected for Operation enabled count clock Operation disabled (display off mode set before disabling) Operation stopped Interrupt request signals (except INT0, INT1, and INT2) from operable hardware enabled by interrupt enable flags, or RESET input.
FIP controller/driver CPU Release signal
26
PD75218
8. RESET FUNCTIONS
The reset signal (RES) generator has a configuration shown in Fig. 8-1. Fig. 8-1 Reset Signal Generator
RESET
Internal reset signal (RES)
Fig. 8-2 shows the reset operation. Fig. 8-2 Reset Operation by RESET Input
Wait
(21.8 ms/when the microcomputer operates at 6.0 MHz)Note
RESET input
Normal operation mode or standby mode
HALT mode
Normal operation mode
Internal reset operation
Note
31.3 ms when the microcomputer operates at 4.19 MHz
Table 8-1 lists the hardware statuses after reset operation.
27
PD75218
Table 8-1 Hardware Statuses after Reset Operation
Hardware Program counter (PC) RESET input in standby mode Set the low-order six bits at address 0000H in program memory to PC13-8, set the contents of address 0001H to PC7-0, and set PC14 to zero. Retained 0 0 Set bit 6 of address 0000H in program memory to RBE and set bit 7 to MBE. Undefined Undefined RetainedNote Retained 0, 0 Undefined 0 0 FFH 0 Retained 0 0 Retained Set bit 4 to 1 and other bits to 0. 0 0 Reset (0) 0 0 0, 0 Off Cleared (0) 0 Retained 0 1000B 0 Retained Off RESET input during operation Set the low-order six bits at address 0000H in program memory to PC13-8, set the contents of address 0001H to PC7-0, and set PC14 to zero. Undefined 0 0 Set bit 6 of address 0000H in program memory to RBE and set bit 7 to MBE. Undefined Undefined Undefined Undefined 0, 0 Undefined 0 0 FFH 0 Undefined 0 0 Undefined Set bit 4 to 1 and other bits to 0. 0 0 Reset (0) 0 0 0, 0 Off Cleared (0) 0 Undefined 0 1000B 0 Undefined Off
PSW
Carry flag (CY) Skip flag (SK0-SK2) Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE)
Stack pointer (SP) Stack bank selection register (SBS) Data memory (RAM) General register (X, A, H, L, D, E, B, C) Bank selection register (MBS, RBS) Basic interval timer Counter (BT) Mode register (BTM) Timer/event counter Counter (T0) Modulo register (TMOD0) Mode register (TM0) Timer/pulse generator Clock timer Serial interface Modulo register (MODH, MODL) Mode register (TPGM) Mode register (WM) Shift register (SIO) Mode register (SIOM) Clock generator Processor clock control register (PCC) System clock control register (SCC) Interrupt Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Priority specification flag (IPS) INT0/INT1 mode register (IM0, IM1) Digital port Output buffer Output latch
I/O mode register (PMGA, PMGB)
PORT H FIP controller/driver
Output latch Display mode register (DSPM) Digit selection register (DIGS)
Dimmer selection register (DIMS)
Display data memory Output buffer
Note 28
Data from address 0F8H to address 0FDH in the data memory becomes undefined by RESET input.
PD75218
9. INSTRUCTION SET
(1) Representation format and description method of operands An operand is described in the operand field of each instruction according to the description method corresponding to the operand representation format of the instruction (refer to "RA75X Assembler Package User's Manual, Language" (EEU-1363) for details). When two or more elements are described in the description method field, select one of them. Uppercase letters, a plus sign (+), and a minus sign (-) are keywords, so they can be used without alteration. Specify an appropriate numeric value or label for immediate data.
Representation format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr1 addr caddr faddr taddr PORTn IExxx RBn MBn
Description method X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H-FBFH/FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-7F7FH immediate data or label 0000H-3F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (bit 0 = 0) or label PORT0-PORT6 IEBT, IESIO, IET0, IETPG, IE0, IE1, IEKS, IEW, IE4 RB0-RB3 MB0, MB1, MB2, MB3, MB15
Note
Only even addresses can be specified for 8-bit data processing.
29
PD75218
(2) Legend A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE IME IPS RBS MBS PCC . (xx) xxH : A register, 4-bit accumulator : B register, 4-bit accumulator : C register, 4-bit accumulator : D register, 4-bit accumulator : E register, 4-bit accumulator : H register, 4-bit accumulator : L register, 4-bit accumulator : X register, 4-bit accumulator : Register pair (XA), 8-bit accumulator : Register pair (BC), 8-bit accumulator : Register pair (DE), 8-bit accumulator : Register pair (HL), 8-bit accumulator : Extended register pair (XA') : Extended register pair (BC') : Extended register pair (DE') : Extended register pair (HL') : Program counter : Stack pointer : Carry flag, bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Interrupt master enable flag : Interrupt priority specification register : Register bank select register : Memory bank select register : Processor clock control register : Address/bit delimiter : Contents addressed by xx : Hexadecimal data
PORTn : Port n (n = 0 to 6)
IExxx : Interrupt enable flag
30
PD75218
(3) Explanation of the symbols in the addressing area field
*1
MB = MBE*MBS (MBS = 0, 1, 2, 3, or 15) MB = 0 MBE = 0: MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1: MB = MBS (MBS = 0, 1, 2, 3, or 15) MB = 15, fmem = FB0H-FBFH or FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-3F7FH addr = (Current PC) - 15 to (Current PC) - 1 or (Current PC) + 2 to (Current PC) + 16 caddr = 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3FFFH 4000H-4FFFH 5000H-5FFFH 6000H-6FFFH 7000H-7F7FH faddr = 0000H-07FFH taddr = 0020H-007FH addr1 = 0000H-7F7FH (PC14,13,12 (PC14,13,12 (PC14,13,12 (PC14,13,12 (PC14,13,12 (PC14,13,12 (PC14,13,12 (PC14,13,12 = = = = = = = = 000B) 001B) 010B) 011B) 100B) 101B) 110B) 111B) or or or or or or or Data memory addressing
*2 *3
*4
*5 *6 *7
*8
Program memory addressing
*9 *10 *11
Remarks 1. 2. 3. 4.
MB indicates an accessible memory bank. For *2, MB is always 0 irrespective of MBE and MBS. For *4 and *5, MB is always 15 irrespective of MBE and MBS. *6 to *11 indicate each addressable area.
(4) Explanation of the machine cycle column S represents the number of machine cycles required when a skip instruction with the skip function performs a skip operation. S assumes one of the following values: * When no skip operation is performed * When a 3-byte instruction is skipped Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of the CPU clock (= tCY), and three types of times are available for selection according to the PCC setting. : S=0 : S=2
* When a 1-byte instruction or 2-byte instruction is skipped : S = 1
31
PD75218
Instruction Mnemonic Transfer MOV
Operand A,#n4 reg1,#n4 XA,#n8 HL,#n8 rp2,#n8 A,@HL A,@HL+ A,@HLA,@rpa1 XA,@HL @HL,A @HL,XA A,mem XA,mem mem,A mem,XA A,reg XA,rp' reg1,A rp'1,XA
Number Machine of bytes cycle
Operation A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC14-8+DE)ROM XA (PC14-8+XA)ROM XA (BCDE)ROM XA (BCXA)ROM
Addressing area
Skip condition String effect A
1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1
1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3
String effect A String effect B
*1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH
XCH
A,@HL A,@HL+ A,@HLA,@rpa1 XA,@HL A,mem XA,mem A,reg1 XA,rp'
*1 *1 *1 *2 *1 *3 *3 L=0 L = FH
Table reference
MOVT
XA,@PCDE XA,@PCXA XA, @BCDE XA, @BCXA
*11 *11
32
PD75218
Instruction Mnemonic Bit transfer MOV1
Operand CY,fmem.bit CY,pmem.@L CY,@H+mem.bit fmem.bit,CY pmem.@L,CY @H+mem.bit,CY
Number Machine of bytes cycle
Operation CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A + n4 XA XA + n8 A A + (HL) XA XA + rp' rp'1 rp'1 + XA A,CY A + (HL) + CY XA,CY XA + rp' + CY rp'1,CY rp'1 + XA + CY A A - (HL) XA XA - rp' rp'1 rp'1 - XA A,CY A - (HL) - CY XA,CY XA - rp' - CY rp'1,CY rp'1 - XA - CY
Addressing area
Skip condition
2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2
2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2
*4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1
Arithmetic/logical
ADDS
A,#n4 XA,#n8 A,@HL XA,rp' rp'1,XA
ADDC
A,@HL XA,rp' rp'1,XA
SUBS
A,@HL XA,rp' rp'1,XA
*1
borrow borrow borrow
SUBC
A,@HL XA,rp' rp'1,XA
*1
AND
A,#n4 A,@HL XA,rp' rp'1,XA
AA
AA XA XA
n4 (HL) *1
rp'
rp'1 rp'1 AA
XA
OR
A,#n4 A,@HL XA,rp' rp'1,XA
XOR
A,#n4 A,@HL XA,rp' rp'1,XA
n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA
CY A0, A3 CY, An-1 An AA
*1
*1
Accumulator manipulation
RORC NOT
A A
33
PD75218
Instruction Mnemonic Increment/ INCS decrement reg rp1
Operand
Number Machine of bytes cycle
Operation reg reg + 1 rp1 rp1 + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 rp' rp' - 1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY
Addressing area
Skip condition reg = 0 rp1 = 00H
1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1
1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1
@HL mem DECS reg rp' Comparison SKE reg,#n4 @HL,#n4 A,@HL XA,@HL A,reg XA,rp' Carry flag manipulation SET1 CLR1 SKT NOT1 CY CY CY CY
*1 *3
(HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4
*1 *1 *1
(HL) = n4 A = (HL) XA = (HL) A = reg XA = rp'
CY = 1
34
PD75218
Instruction Mnemonic SET1 Memory bit manipulation
Operand mem.bit fmem.bit pmem.@L @H+mem.bit
Number Machine of bytes cycle
Operation (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2+L3-2.bit(L1-0)) = 1 Skip if (H+mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2+L3-2.bit(L1-0)) = 0 Skip if (H+mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear
Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear
Addressing area
Skip condition
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 --
2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 --
*3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *11
(mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1
(@H+mem.bit) = 1
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
(mem.bit) = 0 (fmem.bit) = 0
(pmem.@L) = 0
(@H+mem.bit) = 0
SKTCLR
fmem.bit pmem.@L @H+mem.bit
(fmem.bit) = 1 (pmem.@L) = 1
(@H+mem.bit) = 1
Skip if (H+mem3-0.bit) = 1 and clear
AND1
CY,fmem.bit CY,pmem.@L CY,@H+mem.bit
OR1
CY,fmem.bit CY,pmem.@L CY,@H+mem.bit
XOR1
CY,fmem.bit CY,pmem.@L CY,@H+mem.bit
(fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit)
CY CY PC14-0 addr1
(The assembler selects an appropriate instruction from the BR !addr, BRA !addr1, BRCB !caddr, and BR $addr instructions.)
Branch
BR
addr1
$addr !addr PCDE PCXA BCDE BCXA BRA BRCB !addr1 !caddr
1 3 2 2 2 2 3 2
2 3 3 3 3 3 3 2
PC14-0 addr PC14 0, PC13-0 !addr PC14-0 PC14-8 + DE PC14-0 PC14-8 + XA PC14-0 BCDE PC14-0 BCXA PC14-0 !addr1 PC14-0 PC14,13,12 + caddr11-0
*7 *6
*11 *8
35
PD75218
Instruction Mnemonic Subroutine stack control CALL
Operand !addr
Number Machine of bytes cycle
Operation (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0,PC14,PC13, PC12 (SP-2) x,x,MBE,RBE PC14 0, PC13-0 addr, SP SP - 6
Addressing area
Skip condition
3
4
*6
CALLA
!addr1
3
3
(SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0,PC14,PC13, PC12 (SP-2) x,x,MBE,RBE PC14-0 addr1, SP SP - 6 (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0,PC14,PC13, PC12 (SP-2) x,x,MBE,RBE PC14-0 0000, faddr, SP SP - 6 x,x,MBE,RBE (SP+4) PC11-0 (SP)(SP+3)(SP+2) x,PC14,PC13,PC12 (SP+1) SP SP + 6 x,x,MBE,RBE (SP+4) PC11-0 (SP)(SP+3)(SP+2) x,PC14,PC13,PC12 (SP+1) SP SP + 6 then skip unconditionally x,PC14,PC13,PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP + 6 (SP-1)(SP-2) rp, SP SP - 2 (SP-1) MBS, (SP-2) RBS, SP SP - 2 rp (SP+1)(SP), SP SP + 2 MBS (SP+1), RBS (SP), SP SP + 2 IME(IPS.3) 1 IExxx 1 IME(IPS.3) 0 IExxx 0 A PORTn (n=0 to 6) XA PORTn+1,PORTn (n=4) PORTn A (n=2 to 6) PORTn+1,PORTn XA (n=4)
*11
CALLF
!faddr
2
3
*9
RET
1
3
RETS
1
3+S
Unconditionally
RETI
1
3
PUSH
rp BS
1 2
1 2
POP
rp BS
1 2
1 2
Interrupt control
EI IExxx DI IExxx
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
I/O
INNote
A,PORTn XA,PORTn
OUTNote
PORTn,A PORTn,XA
Note
MBE = 0, or MBE = 1 and MBS = 15 must be set when an IN/OUT instruction is executed.
36
PD75218
Instruction Mnemonic CPU control HALT STOP NOP Special SEL
Operand
Number Machine of bytes cycle
Operation Set HALT mode (PCC.2 1) Set STOP mode (PCC.3 1) No operation RBS n (n=0-3) MBS n (n=0,1,2,3,15) * For a TBR instruction PC13-0 (taddr)5-0 + (taddr+1) PC14 0 * For a TCALL instruction (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0, PC14, PC13, PC12 (SP-2) x,x,MBE,RBE PC13-0 (taddr)5-0 + (taddr+1) SP SP-6 PC14 0 * For an instruction other than TBR and TCALL Executes the instruction in (taddr)(taddr+1).
Addressing area
Skip condition
2 2 1 RBn MBn 2 2 1
2 2 1 2 2 3
GETINote
taddr
*10
4
3
Depends upon the referenced instruction.
Note
The TBR and TCALL instructions are table definition assembler pseudo instructions of the GETI instructions.
37
PD75218
10. MASK OPTION SELECTION
The PD75218 has the following mask options enabling or disabling on-chip components.
Pin P60 to P63 T0/T9 T10/S15/PH3 to T13/S12/PH0 T14/S11, T15/S10 S0 to S9 XT1, XT2 The feedback resistor for the subsystem clock oscillator can be removed Mask option Pull-up resistor incorporation enabled in bit units
Cautions 1. In a system not using subsystem clocks, power consumption in the STOP mode can be decreased by removing the feedback resistor from the oscillator. 2. The feedback resistor must be incorporated when the subsystem clock is used.
38
PD75218
11. APPLICATION BLOCK DIAGRAM
11.1 VCR TIMER TUNER
Main power supply
+ Super capacitor
Power failure detection
VDD INT4
VSS T0-T9 10
Electronic tuner
LPF
PPO
PD75218
Timer Tuner Remote controller INT1 signal reception Tape counter SCK SO
S0-S15 16
Fluorescent indication panel (FIP) 16 segments x 10 digits
Tape count pulse Tape up/down SCK System controller SO microcomputer SI
PORT6
Key matrix (16 x 4)
PD75104 or PD75106
EEPROMTM PD6252 PD6253 PD6254
INT0
Remote-controller signal
PC2800A
BUZ X1 X2 XT1 XT2 BZ Piezoelectric buzzer
39
PD75218
11.2 COMPACT DISK PLAYER
Servo control IC
SIO
SCK SI/SO
T0-T13 14
S0-S11 12
Fluorescent indication panel (FIP) 12 segments x 14 digits
Loading circuit
PD75218
Key matrix (12 x 4)
PORT6 BUZ BZ INT0
Remote-controller signal
PC2800A
X1 X2
40
PD75218
11.3 ECR
Main power supply
+
Power failure detection
VDD INT4
VSS T0-T15 16
S0-S9 10 RAM
Fluorescent indication panel (FIP) 10 segments x 16 digits
PD75218
Key matrix (10 x 4) Printer
PPO BZ X1 X2 XT1 XT2
41
PD75218
5
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
Parameter Symbol VDD Power supply voltage VLOAD VPRE Input voltage Output voltage VOD Display output pins Per pin except display output pins Per pin for S0 to S9 Output high current IOH Per pin for T0 to T15 Total of pins except display output pins Total of display output pins Output low current IOL Per pin Total of pins Total lossNote 1 Operating temperature Storage temperature PT Topt Tstg Plastic QFP Plastic shrink DIP VDD - 40 to VDD + 0.3 -15 -15 -30 -20 -120 17 60 450 600 -40 to +85 -65 to +150 V mA mA mA mA mA mA mA mW mW C C VI VO Pins except display output pins Conditions Rating -0.3 to +7.0 VDD - 40 to VDD + 0.3 VDD - 11 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 Unit V V V V V
OPERATING SUPPLY VOLTAGE (Ta = -40 to +85 C)
Parameter CPUNote 2 Display controller Timer/pulse generator Other hardwareNote 2 Conditions Min.
Note 3
Max. 6.0 6.0 6.0 6.0
Unit V V V V
4.5 4.5 2.7
42
PD75218
Notes 1. Calculation of total loss Design so that the sum of the following three power consumption values for the PD75218CW/GF will be less than the total loss PT (It is recommended to use the system with 80 % or less of the rating). CPU loss : Given as VDD (Max.) x IDD1 (Max.) Output pin loss : There are normal output pin loss and display output pin loss. It is necessary to add a loss derived from the flow of maximum current to each output pin. Pull-down register loss: Power loss due to a pull-down resistor incorporated in the display output pin by mask option.
Example
Suppose 4-LED output with 9 segments and 11 digits, VDD = 5 V + 10 % and 4.19 MHz oscillation and let a maximum of 3 mA, 15 mA and, 10 mA flow to a segment pin, timing pin and LED output pin, respectively. Further, let the voltage of fluorescent display tube (VLOAD voltage) be -30 V and normal voltage be small. CPU loss : 5.5 V x 9.0 mA = 49.5 mW Pin loss : Segment pin ..... 2 V x 3 mA x 9 = 54 mW Timing pin ......... 2 V x 15 mA = 30 mW LED output ........ 10 x2V 15 x 10 mA x 4 = 53 mW
2 Pull-down resistor loss ........ (30 + 5.5 V) x 10 = 504.1 mW 25 k
PT = + + = 690.6 mW In this example, the power consumption of 690.6 mW is higher than the allowable total loss for the shrink DIP package (600 mW). It is necessary to decrease power consumption by decreasing the number of onchip pull-down resistors. In this example, power consumption can be adjusted to 577.8 mW by incorporating pull-down resistors in only 11 digit outputs and 7 segment outputs and externally mounting pull-down resistors to the 2 remaining segment outputs. 2. Except the system clock oscillator, display controller and timer/pulse generator. 3. The operating voltage range varies depending on the cycle time. Refer to the AC characteristics. CAPACITANCE (Ta = 25 C, VDD = 0 V)
Parameter Input capacitance Except display output Output capacitance Display output Input /output capacitance CIO COUT Symbol CIN f = 1 MHz 0 V for pins other than pins to be measured Conditions Min. Typ. Max. 15 15 35 15 Unit pF pF pF pF
43
PD75218
CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Ceramic resonator
Note 3
Recommended constants
X1 X2
Parameter Oscillator frequency (fXX) Note 1
Conditions VDD = Oscillation voltage range After VDD reaches Min. of the oscillation voltage range
Min. 2.0
Typ.
Max. 6.2
Unit MHz
C1
C2
Oscillation settling time
Note 2
4
ms
Crystal resonator
Note 3
X1
X2
Oscillator frequency (fXX) Note 1
C2
2.0
4.19
6.2
MHz
C1
Oscillation settling time
Note 2
VDD = 4.5 to 6.0 V
10 30 2.0 6.2
ms ms MHz
External clock
X1
X2
X1 input frequency (fX) Note 1 X1 input high/low level width (tXH, tXL)
100
250
ns
PD74HCU04
Notes 1. 2. 3.
The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. The oscillation settling time means the time required for the oscillation to settle after VDD reaches Min. of the oscillation voltage range or after the STOP mode is released. See "Recommended Parameters for the Oscillation Circuit" for the resonators.
Caution When the main system clock oscillator is used, conform to the following guidelines when wiring at the portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. * The wiring must be as short as possible. * Other signal lines must not run in these areas. Any line carrying a high fluctuating current must be kept away as far as possible. * The grounding point of the capacitor of the oscillator must have the same potential as that of VDD. It must not be grounded to ground patterns carrying a large current. * No signal must be taken from the oscillator.
44
PD75218
CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Crystal resonator
Note 3
Recommended constants
Parameter Oscillator frequency (fXT) Note 1 Oscillation settling time
Note 2
Conditions
Min. 32
Typ. 32.768
Max. 35
Unit kHz
XT1
XT2 330 k
VDD = 4.5 to 6.0 V
1.0
2 10
s s
C3 VDD
External clock
XT1 XT2
C4
Leave open
XT1 input frequency (fXT) XT1 input high/low level width (tXTH, tXTL)
32
100
kHz
10
32
s
Notes 1. 2. 3.
The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. The oscillation settling time means the time required for the oscillation to settle after VDD reaches Min. of the oscillation voltage range. Recommended resonators are listed on the next page.
Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring at the portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. * The wiring must be as short as possible. * Other signal lines must not run in these areas. Any line carrying a high fluctuating current must be kept away as far as possible. * The grounding point of the capacitor of the oscillator must have the same potential as that of VDD. It must not be grounded to ground patterns carrying a large current. * No signal must be taken from the oscillator. When the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator has low amplification to minimize current consumption and is more likely to malfunction due to noise than the main system clock oscillator.
45
PD75218
RECOMMENDED PARAMETERS FOR THE OSCILLATION CIRCUIT When a ceramic resonator is used for the main system clock (Ta = -40 to +70 C)
Manufacturer Murata Mfg. External capacitance Oscillation voltage Oscillation frequency (pF) range (V) (MHz) Min. C1 C2 Max. 2.00 to 2.44 30 Built-in 2.45 to 3.50 30 Built-in 2.51 to 6.00 30 Built-in 2.45 to 3.50 30 Built-in 2.51 to 6.00 30 Built-in 30 Built-in 30 Built-in 30 Built-in 30 Built-in 30 Built-in 3.3 3.0 2.7 6.0
Product name CSAxxxMG CSTxxxMG CSAxxxMG093 CSTxxxMGW093 CSAxxxMGU CSTxxxMGWU CSAxxxMG CSTxxxMGW CSAxxxMG CSTxxxMGW
When a ceramic resonator is used for the main system clock (Ta = -20 to +80 C)
Manufacturer Kyocera External capacitance Oscillation voltage Oscillation frequency (pF) range (V) (MHz) Min. C1 C2 Max. 2.0 4.0 4.19 47 33 Built-in 33 Built-in 33 6.0 Built-in 33 Built-in 33 47 33 Built-in 33 Built-in 33 Built-in 33 Built-in 33 2.7 6.0
Product name KBR-2.0MS KBR-4.0MWS KBR-4.19MWS KBR-4.19MSA KBR-4.19MKS PBRC 4.19A KBR-6.0MWS KBR-6.0MSA KBR-6.0MKS PBRC 6.00A
When a crystal resonator is used for the main system clock (Ta = -20 to +70 C)
External capacitance Oscillation voltage Oscillation frequency (pF) range (V) (MHz) Min. C1 C2 Max. 3.072 to 6.000 18 18 2.7 6.0
Manufacturer Kinseki
Product name HC-49/U-S
When a crystal resonator is used for the subsystem clock (Ta = -15 to +60 C)
Oscillation frequency (MHz) 32.768 External capacitance and resistance
C1 (pF) C2 (pF)
Manufacturer Kyocera
Product name KF-38G
R (k) 220
Oscillation voltage range (V) Min. Max. 4.0 6.0
18
18
Caution When finely adjusting the oscillation frequency of a crystal resonator, adjust external capacitance C1 or C3. 46
PD75218
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter Input high voltage Symbol VIH1 VIH2 VIH3 VIH4 Except below Ports 0, 1, RESET X1, X2, XT1 Port 6 VDD = 4.5 to 6.0 V Conditions
Min. 0.7VDD 0.75VDD VDD-0.4 0.65VDD 0.7VDD
Typ.
Max. VDD VDD VDD VDD VDD 0.3VDD 0.2VDD 0.4
Unit V V V V V V V V V V
Input low voltage
VIL1 VIL2 VIL3
Except below Ports 0, 1, 6, RESET X1, X2, XT1
0 0 0
Output high voltage
VOH
All output pins VDD = 4.5 to 6.0 V, IOH = -1 mA VDD-1.0 IOH = -100 A VDD-0.5 0.5 2.0 0.4 0.5 3 20 -3 -20 3 -3 -10 VNote 1 -3 -1.5 -15 -7 20 20 VOD - VLOAD = 35 V VDD = 5 V 10 VDD = 3 V 10 %Note 3 %Note 4 25 70 4.0 0.55 600 200 3.0 0.45 550 180 40 5 0.5 0.1 -5.5 -3.5 -22 -15 80 200 1000 135 13.5 1.8 1800 600 9.0 1.5 1800 600 120 15 20 10
Output low voltage
VOL
Ports 4, 5
VDD = 4.5 to 6.0 V, IOL = 15 mA
V V V
All output pins VDD = 4.5 to 6.0 V, IOL = 1.6 mA IOL = 400 A Input high leakage current Input low leakage current Output high leakage current Output low leakage current Display output current ILIH1 ILIH2 ILIL1 ILIL2 ILOH ILOL1 ILOL2 IOD Except X1,X2,XT1 VIN = VDD X1, X2, XT1 Except X1,X2,XT1 VIN = 0 V X1, X2, XT1 All output pins VOUT = VDD Except display output VOUT = 0 V Display output S0 to S9 VOUT = VLOAD = VDD - 35 V VDD = VPRE = VDD - 9 1 4.5 to 6.0 V VPRE = 0 V VOD = VPRE = VDD - 9 1 VNote 1 VDD - 2 V VPRE = 0 V VDD = 4.5 to 6.0 V
A A A A A A A
mA mA mA mA k k k mA mA
T0 to T15
Built-in pull-down resistor (mask option)
RP6
Port 6 VIN = VDD Display output 6.0 MHz crystal oscillation C1 = C2 = 15pF
RL Supply currentNote 2 IDD1
IDD2
HALT mode VDD = 5 V 10 % VDD = 3 V 10 %
A A
mA mA
IDD1
4.19 MHz crystal oscillation C1 = C2 = 15pF
VDD = 5 V 10 VDD = 4 V 10
%Note 3 %Note 4
IDD2
HALT mode VDD = 5 V 10 % VDD = 3 V 10 %
A A A A A A
IDD3 IDD4 IDD5
VDD = 3 V 10 % 32 kHz crystal oscillationNote 5 HALT mode VDD = 3 V 10 % XT1 = 0 V STOP mode VDD = 5 V 10 % VDD = 3 V 10 %
47
PD75218
Notes 1.
The following external circuit is recommended.
PD75218
+5 V VDD RD9. 1EL VPRE 68 k VLOAD -30 V VSS RD9. 1EL : Zener diode (NEC) Zener voltage = 8.29 to 9.30 V
2. Current to the on-chip pull-down resistor (mask option) is not included. 3. When the processor clock control register (PCC) is set to 0011 and is operated in the high-speed mode. 4. When the PCC register is set to 0000 and is operated in the low-speed mode. 5. When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock with main system clock oscillation stopped.
48
PD75218
AC CHARACTERISTICS (Ta = -40 to +85 C , VDD = 2.7 to 6.0 V)
Parameter CPU clock cycle time (minimum instruction execution time = 1 machine cycle)Note 1 TI0 input frequency Symbol tCY Conditions Operation with main system clock Operation with subsystem clock fTI VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V Min. 0.67 2.6 114 0 0 TI0 input high and lowlevel widths SCK cycle time tTIH, tTIL tKCY VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V Input Output Input Output SCK high and low-level widths tKH, tKL VDD = 4.5 to 6.0 V Input Output Input Output SI setup time (referred to SCK) SI hold time (referred to SCK) Delay from SCK to SO output Interrupt input high and low-level widths tSIK tKSI tKSO VDD = 4.5 to 6.0 V 0.83 3 0.8 0.95 3.2 3.8 0.4 tKCY/2-50 1.6 tKCY/2-150 100 122 Typ. Max. 32 32 125 0.6 165 Unit
s s s
MHz kHz
s s s s s s s
ns
s
ns ns
400 300 1000
ns ns ns
tINTH, tINTL
INT0 INT1 INT2, INT4
Note 2
s s s s
2tCY 10 10
RESET low-level width
tRSL
Notes 1.
CPU clock () cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (SCC) and the processor clock control register (PCC). The cycle time tCY characteristics for power supply voltage VDD when the main system clock is in operation is shown on the right.
Cycle time tCY [ s]
tCY
40 32 30 6 5 4 3
VS
VDD
(Operation with main system clock)
Guaranteed operation range
2.
2tCY or 128/fXX is set by interrupt mode register (IM0) setting.
2
1
0.5 0 1 2 3 4 5 6
Power supply voltage VDD [V]
49
PD75218
AC Timing Measurement Values (Except X1 and XT1 Inputs)
0.75VDD 0.2VDD
Test points
0.75VDD 0.2VDD
Clock Timing
1/fX tXL tXH
X1 input
VDD - 0.4 V 0.4 V
1/fXT tXTL tXTH
XT1 input
VDD - 0.4 V 0.4 V
TI0 Timing
1/fTI tTIL tTIH
TI0
50
PD75218
Serial Transfer Timing
tKCY tKL tKH
SCK
tSIK
tKSI
SI
Input data
tKSO
SO
Output data
Interrupt Input Timing
tINTL
tINTH
INT0, INT1, INT2 and INT4
RESET Input Timing
tRSL
RESET
51
PD75218
DATA RETENTION CHARACTERISTICS FOR DATA MEMORY AT LOW SUPPLY VOLTAGE IN STOP MODE (Ta = -40 to +85 C)
Parameter
Data retention supply voltage
Data retention supply currentNote 1
Symbol VDDDR IDDDR tSREL tWAIT Release by RESET VDDDR = 2.0 V
Conditions
Min. 2.0
Typ.
Max. 6.0
Unit V
0.1 0 217/fX
Note 3
10
A s
ms ms
Release signal set time Oscillation settling timeNote 2
Release by interrupt request
Notes 1. 2. 3.
Current to the on-chip pull-down resistor (mask option) is not included. Oscillation settling time is time to stop CPU operation to prevent unstable operation upon oscillation start. According to the setting of the basic interval timer mode register (BTM) (See below.)
BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 Settling time (values at fXX = 6.0 MHz in parentheses) 220/fXX (approx. 175 ms) 217/fXX (approx. 21.8 ms) 215/fXX (approx. 5.46 ms) 213/fXX (approx. 1.37 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode Normal operation mode
STOP mode Data retention mode
VDD VDDDR STOP instruction execution tSREL
RESET tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode Normal operation mode
STOP mode Data retention mode
VDD STOP instruction execution Standby release signal (Interrupt request)
VDDDR
tSREL
tWAIT
52
PD75218
13. CHARACTERISTIC CURVES (FOR REFERENCE)
IDD vs VDD (Main system clock: 6.0 MHz)
(Ta = 25 C)
5
5000
PCC = 0011 PCC = 0010
PCC = 0000 Main system clock HALT mode + 32 kHz oscillation
1000
500
Supply current IDD ( A)
Subsystem clock Normal operation mode 100
50 Main system clock STOP mode + 32 kHz oscillation Subsystem clock HALT mode
10
X1 X2 Crystal resonator 6.0 MHz 15 pF 15 pF XT1 XT2 Crystal resonator 32.768 kHz 330 k 15 pF 15 pF
5
1 0 1 2 3 4 5 6 7 Supply voltage VDD (V)
53
PD75218
IDD vs VDD (Main system clock: 4.19 MHz)
(Ta = 25 C)
5000 PCC = 0011 PCC = 0010
PCC = 0000 1000 Main system clock HALT mode + 32 kHz oscillation
500
Supply current IDD ( A)
Subsystem clock Normal operation mode 100
50 Main system clock STOP mode + 32 kHz oscillation Subsystem clock HALT mode
10
X1 X2 Crystal resonator 4.19 MHz 15 pF 15 pF XT1 XT2 Crystal resonator 32.768 kHz 330 k 15 pF 15 pF
5
1 0 1 2 3 4 5 6 7 Supply voltage VDD (V)
54
PD75218
14. PACKAGE DIMENSIONS
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
55
PD75218
64 PIN PLASTIC QFP (14x20)
A B
51 52
33 32
detail of lead end
C
D
S
Q R
64 1
20 19
F G
H
I
M
J
K P N L M
NOTE
Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 1.0 1.0 0.400.10 0.20 1.0 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05
INCHES 0.9290.016 0.795 +0.008 -0.009 0.551+0.009 -0.008 0.6930.016 0.039 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003
0.10 0.004 2.7 0.106 0.10.1 0.0040.004 55 55 3.0 MAX. 0.119 MAX. P64GF-100-3B8,3BE,3BR-2
56
PD75218
15.
RECOMMENDED SOLDERING CONDITIONS
The following conditions (see table below) must be met when soldering this product. For the details of the recommended soldering conditions refer to our document SMD Surface Mount Technology Manual(IEI-1207). Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. Table 15-1 Soldering Conditions for Surface-Mount Devices
PD75218GF-xxx-3BE: 64-pin plastic QFP (14 x 20 mm)
Soldering process Wave soldering Soldering conditions Temperature in the soldering vessel: 260 C or less Soldering time: 10 seconds or less Number of soldering processes: 1 Pre-heating temperature: 120 C max. (package surface temperature) Exposure limitNote: 2 days (20 hours of pre-baking is required at 125 C afterward.) Peak package's surface temperature: 230 C Reflow time: 30 seconds or less (at 210 C or more) Number of reflow processes: 1 Exposure limitNote: 2 days (20 hours of pre-baking is required at 125 C afterward.) Peak package's surface temperature: 215 C Reflow time: 40 seconds or less (at 200 C or more) Number of reflow processes: 1 Exposure limitNote: 2 days (20 hours of pre-baking is required at 125 C afterward.) Terminal temperature: 300 C or less Flow time: 3 seconds or less (one side per device) Symbol WS60-202-1
Infrared ray reflow
IR30-202-1
VPS
VP15-202-1
Partial heating method
-
Note
Exposure limit before soldering after dry-pack package is opened. Storage conditions: Temperature of 25 C and maximum relative humidity at 65 % or less Do not apply more than a single process at once, except for "Partial heating method." Table 15-2 Soldering Conditions for Inserted Devices
Caution
PD75218CW-xxx: 64-pin plastic shrink DIP (750 mil)
Soldering process Wave soldering (only for leads) Partial heating method Soldering conditions Temperature in the soldering vessel: 260 C or less Soldering time: 10 seconds or less Terminal temperature: 260 C or less Flow time: 10 seconds or less
Caution In wave soldering, apply solder only to the lead section. Care must be taken that jet solder does not contact the main body of the package. Notice Other versions of the products are available. For these versions, the recommended reflow soldering conditions have been mitigated as follows: Higher peak temperature (235 C), two-stage, and longer exposure limit. Contact an NEC representative for details. 57
PD75218
APPENDIX A FUNCTIONS OF PD752xx SERIES PRODUCTS
PD75218
32640 x 8 1024 x 4 0.67 s/1.33 s/10.7 s (When the microcomputer operates at 6.0 MHz) 0.95 s/1.91 s/15.3 s (When the microcomputer operates at 4.19 MHz)
Item ROM RAM Instruction cycle When main system clock is selected
PD75216A
16256 x 8 512 x 4
PD75217
24448 x 8 768 x 4
PD75P218
0.95 s/1.91 s/15.3 s (When the microcomputer operates at 4.19 MHz)
When sub-system clock is selected I/O lines including FIP dualfunction pins and excluding FIP dedicated pins Total number of I/O lines CMOS input lines CMOS I/O lines
122 s (When the microcomputer operates at 32.768 kHz) 33 8 20: 8 lines for driving LED Port 6: Pull-down resistors contained (mask option) Port 6: No pull-down resistors contained
CMOS output lines P-ch open-drain output with high withstand voltage and high current FIP controller/ driver Output with high withstand voltage
1: Timer/pulse generator output 4 lines for driving LED: (mask option) Pull-down resistors contained No pull-down resistors contained
26 lines: 40 V max. Whether built-in pull-down resistors are used or the pins are used as open-drain output is selected bit by bit (mask option). S0-S8,T0-T9: Built-in pull-down resistors used S9,T10-T15: Open-drain output
Number of segments Number of digits Timer
9 to 16 9 to 16 4 channels * * * * Timer/event counter Basic interval timer : Watchdog timer operation is possible. Timer/pulse generator : 14-bit PWM output is possible. Watch timer : Buzzer output is possible.
Serial interface Vectored interrupt Test input System clock oscillator
MSB or LSB first can be selected. Serial bus can be configured. External: 3, internal: 5 External: 1, internal: 1 * When main system clock is selected: 6.0 MHz (the PD75218 and PD75P218 only) 4.19 MHz * When subsystem clock is selected: 32.768 kHz None
2 built-in circuits Power-on reset circuit
Data retention at low supply voltage
Incorporated (mask option) Possible (2 V) -40 to +85 C 2.7 to 6.0 V
5
Operating temperature range Operating supply voltage Package
-40 to +70 C
64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 x 20 mm) 64-pin ceramic WQFN (the PD75P218 only)
58
PD75218
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for developing systems including the PD75218:
IE-75000-RNote 1 IE-75001-R IE-75000-R-EMNote 2 EP-75216ACW-R Hardware EP-75216AGF-R EV-9200G-64 PG-1500 PA-75P216ACW PA-75P218GF PA-75P218KB IE control program Software PG-1500 controller RA75X relocatable assembler In-circuit emulator for the 75X series
Emulation board for the IE-75000-R and IE-75001-R Emulation probe for the PD75218CW Emulation probe for the PD75218GF. A 64-pin conversion socket, the EV-9200G-64, is attached to the probe. PROM programmer PROM programmer adapter for the PD75P218CW. Connected to the PG-1500. PROM programmer adapter for the PD75P218GF. Connected to the PG-1500. PROM programmer adapter for the PD75P218KB. Connected to the PG-1500. Host machine * PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00ANote 3) * IBM PC/ATTM (PC DOS TM Ver. 3.1)
Notes 1. Maintenance service only 2. Not contained in the IE-75001-R 3. These software cannot use the task swap function, which is available in MS-DOS Ver. 5.00 and Ver. 5.00A. Remark Refer to "75X Series Selection Guide" (IF-1027) for development tools manufactured by third parties.
59
PD75218
APPENDIX C RELATED DOCUMENTS
Documents related to the device
Document name User's manual 75X series selection guide Document No. IEU-692 IF-1027
Documents related to development tools
Document name IE-75000-R/IE-75001-R User's Manual Hardware IE-75000-R-EM User's Manual EP-75216ACW-R User's Manual EP-75216AGF-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual Operation Language PG-1500 Controller User's Manual
Document No. EEU-1416 EEU-1294 EEU-1321 EEU-1309 EEU-1335 EEU-1346 EEU-1363 EEU-1291
Other related documents
Document name Package Manual SMD Surface Mount Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Document No. IEI-1213 IEI-1207 IEI-1209 IEI-1203 IEI-1201 MEI-1202
Caution The above documents may be revised without notice. Use the latest versions when you design an application system.
60
PD75218
Cautions on CMOS Devices
1 Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. 2 CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediate-level input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. 3 Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first.
61
PD75218
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
EEPROM is a trademark of NEC Corporation. FIP is a trademark of NEC Corporation. MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are a trademarks of IBM Corporation.

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